A field-programmable gate array (“FPGA”) is an integrated circuit (“IC”) that can be programmed in the field after manufacture. FPGAs typically contain programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinatorial functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories. A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term “field programmable”) so that the FPGA can perform whatever logical function is needed.
An example of a FPGA is the Virtex™-4 FPGA from Xilinx™. The Virtex™-4 FPGA has a feature called “ChipSync Technology” which simplifies implementation of source-synchronous interfaces. For reference, a source-synchronous system is a system that uses a clock signal generated by the address/data signal source (e.g., the FPGA) to latch or clock the address/data signals at the receiving agent (e.g., a random access memory (“RAM”) device such as a quad data rate (QDR™II) synchronous RAM (“SRAM”) device or a reduced latency dynamic random access memory (“RLDRAM”) device). Implementing a self-timed clock at the receiver eliminates the flight time variable from system timing equations. Eliminating flight time allows the designer to maximize the potential bandwidth of any interface technology by increasing the operating frequency. Because interface signal timing is now working in “relative” time, the global skew requirements of the system clock are reduced.
Thus, in a source-synchronous interface the clock is usually sent along with the data. The FPGA uses the clock to recover the data. For high speed SRAMs like a QDR™II SRAM, a clock is sent to the QDR™II device and data is returned along with a re-generated clock. This returned clock will be delayed with respect to the original clock (i.e., the FPGA system clock). Read data can easily be recovered using the returned clock, but getting the data back into synchronization with the system clock is another problem. The Xilinx “ChipSync Technology” feature mentioned above solves this problem by delaying the data to align it with the system clock. Thus, the returned clock is not used to recover the data.
At startup, the “ChipSync Technology” feature calibrates the amount of delay needed in order to recover the data back to the system clock of the FPGA. This calibration is intended to offset the delay caused by the board trace length and delay in the FPGA input/output (“IO”) pins. The delay portion caused by the IO is dependant on process and temperature variation. Since the calibration is performed once at start-up, the FPGA may have been at a cold temperature when the calibration was performed. The cold temperature would make the IO delay minimal, but once the FPGA warms up the delay would increase. This is problematic as it reduces timing margins in recovering the data which may cause bit errors.
One solution to this problem is simply to repeat the calibration routine as the FPGA warms up. However, because the data from a double or quad data rate RAM device is both positive and negative clock edge triggered, and due to the dual stream nature of the “ChipSync Technology” circuit (i.e., positive and negative edge triggered data streams), the data may shift 180 degrees out of phase if the calibration routine is run a second time. Such an occurrence may cause data corruption, or data loss, and therefore simply re-running the timing calibration to adjust for delay variances due to temperature variation is not a desirable solution. In addition, simply using a first-in first-out (“FIFO”) buffer device to align the system clock and data is not an option because of the low latency requirements of high speed FPGA applications.
A need therefore exists for an improved method and system for dynamic temperature compensation for a source-synchronous interface between a field-programmable gate array device and a memory device. Accordingly, a solution that addresses, at least in part, the above and other shortcomings is desired.